1. Field of the Invention
The present invention relates to information processing apparatuses and distributed processing control methods and more particularly, to an information processing apparatus and a distributed processing control method in which a plurality of processors are used to perform a distributed load processing.
Examples of information processing apparatuses provided with a plurality of processors are: a dual-redundancy information processing apparatus having an active processor and a standby (reserve) processor so as to produce improved reliability; and an information processing apparatus having a plurality of processors so as to perform processes with improved efficiency. In these information processing apparatuses, there is a demand for adapting to an increase or a reduction in the system scale. Also demanded are provisions for easily remedying a fault.
2. Description of the Related Art
FIG. 1A is a schematic diagram of a conventional electronic switch including a main processor (MPR) 100, call processors (CPR) 101-1-101-n, networks 102-11-102-n, and a bus 103. Each of the networks 102-11-102-n is controlled by the call processors 101-1-101-n, respectively. The call processors 101-1-101-n are controlled by a main processor 100.
The electronic switch having the multi-processor construction described above performs distributed processing of calls. When such an electronic switch is upgraded or repaired, individual call processors or networks may be installed or uninstalled. The call processors 101-1-101-n are managed by the main processor 100. There is also known a construction where each of the call processors 101-1-101-n has a duplex system including an active system and a standby system. The main processor 100 may also have a duplex system. Provision of the duplex system is intended as means for improving the reliability.
The electronic switch may also be constructed such that the switching control function is divided into a plurality of functions and a plurality of processors are provided for each function. When a switching control function is to be executed, one of the plurality of processors is selected in order to execute the target function (see Japanese Laid-Open Patent Application No. 55-53990). In one known distributed load arrangement for processing ATM cells, a plurality of processing apparatuses (processors) for processing ATM cells are connected to a plurality of terminals via interface circuits (see Japanese Laid-Open Patent Application No. 4-179327).
FIG. 1B is a schematic diagram of a conventional ATM switching system suitable for use in a B-ISDN system. A plurality of call processors (CPR) 106-1-106-n, for setting up and releasing an SVC call by controlling a broadband signaling controller described later, are connected between a corresponding one of a plurality of ATM switches 104-1-104-n and a bus 107. A plurality of additional call processors 106'-1-106'-n are coupled to a plurality of additional ATM switches 104'-1-104'-n, respectively, so as to constitute a duplex system. Broadband signaling controllers (BSGC) 105-1-105-n are coupled to the ATM switches 104-1-104-n, respectively, for processing the Layer 2 protocol according to the B-ISDN specification. Additional broadband signaling controllers (BSGC) 105'-1 105'-n are coupled to the additional ATM switches 104'-1-104'-n, respectively, so as to constitute a duplex broadband signaling controller system. A main processor (MPR) 108 is provided to control the entire switching system including the ATM switches. Line interface units 103-1 and 103-2 each accommodates a plurality of circuits. Although not shown, the ATM switches 104-2-104-n and the additional ATM switches 104'-2-104'-n are also coupled to respective line interfaces.
In the conventional ATM switching system as shown in FIG. 1B, call processors 106-1 106-n are fixedly coupled to the respective ATM switches 104-1-104-n. The same thing is true of the additional call processors 106'-1-106'-n, the broadband signaling controllers 105-1-105-n and the additional broadband signaling controllers 105'-1-105'-n. As the volume of data requiring to be processed increases, an increasing volume of load is imposed on each of the call processors and the broadband signaling controllers, causing the number of calls handled by each call processor to be decreased. Such a conventional switching system does not provide means to flexibly distribute required processes among the plurality of call processors.
One approach to resolve this problem is to upgrade the call processor or the broadband signaling controller. However, such a solution invites an associated increase in the cost.
A description will now be given of another disadvantage of the conventional processing system.
In the conventional duplex system including the active system and the standby system, the process can continue in the event of a fault by switching from the active system to the standby system. A system down results when a fault occurs after the standby system is switched to the active system. In the multi-processor distributed load arrangement such as the one shown in FIG. 1A, each of the call processors is fixedly coupled to the corresponding network so that the network governed by a faulty call processor cannot be controlled. Thus, proper service may not be provided due to the fault. Even if the call processors 101-1-101-n have a duplex system, if both the active system and the standby system fail, the network governed by the faulty processors fails to provide the service.
The aforementioned example of the related art (Japanese Laid-Open Patent Application No. 55-53990) in which an extra load is assigned to a free processor selected from a group of processors, each of the processors is assigned to the respective function. Such a system lacks flexibility and requires a selection of a free processor each time a process is requested. In the other example of the prior art (Japanese Laid-Open Patent Application No. 4-179327) where a plurality of processing apparatuses are connected via interface circuits and via a common bus, in order to perform distributed load processing, ATM cells are processed depending on the processing capability of the processors. However, Japanese Laid-Open Patent Application No. 4-179327 does not give any description of a specific manner in which the distributed load processing is executed, nor does it describe processes to be executed in the event of a fault, a system change or the like.